module top_module (
    input clk,
    input reset,     // synchronous reset
    input w,
    output z);
	
	localparam A=3'b000;
	localparam B=3'b001;
	localparam C=3'b010;
	localparam D=3'b011;
	localparam E=3'b100;
	localparam F=3'b101;
	
	reg [2:0]state;
	reg [2:0]next_state;
	
	always@(posedge clk)begin
		if(reset)begin
			state<=A;
		end
		else begin
			state<=next_state;
		end
	end
	
	always@(*)begin
		case(state)
			A:begin
				next_state=(w)?A:B;
			end
			B:begin
				next_state=(w)?D:C;
			end
			C:begin
				next_state=(w)?D:E;
			end
			D:begin
				next_state=(w)?A:F;
			end
			E:begin
				next_state=(w)?D:E;
			end
			F:begin
				next_state=(w)?D:C;
			end
			default:begin
				next_state=next_state;
			end
		endcase
	end
	
	assign z=state==E|state==F;
	
endmodule